1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the invention relates to a semiconductor memory device having a data mask function and a data line shift redundancy function.
2. Description of the Related Art
It has recently been essential for highly integrated semiconductor memory devices to adopt a redundancy technology of replacing a defective cell with a redundant cell. In particular, an embedded DRAM (dynamic random access memory) has a data line shift redundancy function of relieving a defective cell by replacing an internal data line with its adjacent one (see, for example, T. Namekawa et al., “Dynamically Shift-Switched Data Line Redundancy Suitable for DRAM Macro with Wide Data Bus,” 1999 Symposium on VLSI Circuits, Digest of Papers, pp. 149-152)
FIGS. 5A and 5B are diagrams illustrating the main part of a DRAM to describe the above data line shift redundancy function. For the sake of simple descriptions, it is assumed that sixteen input/output data lines are provided for each cell array. Of the input/output lines, only the input data lines DI[i] (i=0, 1, 2, . . . , 15) are shown and the output data lines are omitted because their connections are the same as those of the input data lines DI[i].
Referring to FIG. 5A, input data lines DI[i] to DI[15] of a cell array 100 are connected to their respective sense amplifier (SA) write circuits 102 through a shift switch circuit block (data line shift circuits) 101. When a write signal WE is activated, the SA write circuits 102 write cell data (high “H” or low “L”) of the input data lines DI[0] to DI[15] to their corresponding internal data lines DQt[p] and DQc[p] (or represented together as DQt/c[p]: p=0, 1, 2, . . . , 15) which are complementary to each other. When there are no defective cells as shown in FIG. 5A, the input data lines DI[0] to DI[15] are connected to their respective internal data lines DQt/c[0] to DQt/c[15].
In contrast, when the internal data line DQt/c[2] is defective (cross X) (or a cell connected to the internal data line is defective) as shown in FIG. 5B, the input data line DI[2] that is to be connected to the internal data line DQt/c[2] is shifted by the shift switch circuit block 101 and connected to the internal data line DQt/c[1]. The adjacent input data line DI[1] is connected to the internal data line DQt/c[0] and its adjacent input data line DI[0] is connected to the internal data line DQt/c[15(−1)] of adjacent another cell array 100−1. Thus, the input data lines DI[0] to DI[2] are shifted one by one by the shift switch circuit block 101 and connected to their respective internal data lines DQt/c[p−1].
When the internal data line DQt/c[9] is defective (cross X) (or a cell connected to the internal data line is defective), the input data line DI[9] that is to be connected to the internal data line DQt/c[9] is shifted by the shift switch circuit block 101 and connected to the internal data line DQt/c[10]. The adjacent input data line DI[10] is connected to the internal data line DQt/c[11], . . . , and its adjacent input data line DI[15] is connected to the internal data line DQt/c[0(+1)] of adjacent another cell array 100+1. Thus, the input data lines DI[9] to DI[15] are shifted one by one by the shift switch circuit block, 101 and connected to their respective internal data lines DQt/c[p+1].
In other words, each of the input data lines DI[i] is shifted by the shift switch circuit block 101 such that it is connected to the internal data line DQt/c[p+1] or DQt/c[p−1] adjacent to the internal data line DQt/c[p]. Therefore, the relief of defective cells (data line shift redundancy) can be achieved by replacing the internal data lines DQt/c[p].
FIG. 6 is a diagram illustrating the periphery of the DRAM cell to describe the foregoing data mask function. For the sake of simple descriptions, it is assumed that the number of DRAM cells is one.
As described above, the input/output data line (input data line DI[i] and output data line DO[i]) is connected to the SA write circuit 102a and SA read circuit 102b via the shift switch circuit block 101. The SA write circuit 102a and SA read circuit 102b are supplied with a write signal WE and a read signal RE, respectively. The internal data line DQt/c[p] is connected to the SA write and read circuits 102a and 102b. When the write signal WE is activated, the SA write circuit 102a writes cell data of input data line DI[i] to the internal data line DQt/c[p]. When the read signal RE is activated, the SA read circuit 102b writes cell data of the internal data line DQt/c[p] to the output data line DO/[i].
Bit lines BLt[k] and BLc[k] (or represented together as BLt/c[k]) of complementary signal lines are connected to the internal data line DQt/c[p] through column select transistors 201. A column select signal line CSL[j] is connected to the gate of each of the column select transistors 201. When the column select signal line CSL[j] is activated, the internal data lines DQt/c[p] and bit lines BLt/c[k] are electrically connected to each other. A sense amplifier (SA) 202 is connected to the bit lines BLt/c[k]. The sense amplifier 202 amplifies cell data read out of a memory cell (DRAM cell) 203 and cell data to be written to the memory cell 203.
The memory cell 203 includes a memory cell transistor 203a and a memory cell capacitor 203b. The source of the memory cell transistor 203a is connected to one of the bit lines BLt[k] and BLc[k]. In FIG. 6, the source of the memory cell transistor 203a is connected to the bit line BLt[k]. The drain of the memory cell transistor 203a is connected to one node (storage node) of the memory cell capacitor 203b. The gate of the memory cell transistor 203a is connected to a word line WL[m]. When the word line WL[m] is activated, the memory cell 203 connected to the word line WL[m] is selected (accessed). Thus, the selected memory cell 203 is connected to the SA 202 to read or write cell data. The other node of the memory cell capacitor 203b is connected to the potential VPL.
The data mask signal line DM[n] connected to the SA write circuit 102a and SA read circuit 102b fulfills the above-described data mask function. In other words, it restricts the write of cell data to the internal data line DQt/c[p]. For example, even though the write signal WE is activated in data write mode, the write of cell data to the internal data line DQt/c[p] is considered to be invalid in the SA write circuit 102a in which the data mask signal line DM[n] is activated. In most cases, a single data mask signal line DM[n] is assigned to a plurality of (e.g., eight) input data lines DI[i] in the data mask function.
When the data mask function is added to the DRAM with the data line shift redundancy function, the SA write circuit 102a and SA read circuit 102b have to correspond to different data mask signal lines DM[n] according to the specifications of the data line shift redundancy function. If, therefore, it is assumed that a single data mask signal line DM[n] is assigned to eight input data lines DI[i] as shown in FIG. 7, a shift switch circuit block 301 for data mask (DM) should be provided in correspondence with the data mask signal lines DM[n] and so should be the same number of internal data mask lines DMN[r] (r=0, 1, 2, . . . , 15) as that of input data lines DI [i].
In the DRAM, if the number of input/output data lines DI[i]/DO[i] is large, the same number of internal data mask lines DMN[r] prevent the wiring layers from decreasing in number and increase the power consumption.